1. Field of the Invention
The present invention relates to data control devices for the transfer of digital data and, more particularly, to techniques for phase locked loop data recovery.
2. Description of the Prior Art
With phase-locked loop (PLL) data recovery, a data signal with noise is processed in a PLL circuit so as to eliminate the noise. The processing involves two states, velocity lock and phase lock. During velocity lock, the PLL acquires the data signal, which in a noise-free form is a fixed frequency signal. In order to accomplish velocity lock, the PLL must be supplied with an additional signal consisting of a particular frequency. This fixed signal is typically supplied by a voltage controlled oscillator (VCO). The particular frequency required depends on the application of the PLL. During phase lock, the PLL will decode the data signal which, free of noise, consists of a series of pulses at varying frequencies. The pulse frequencies are integer multiples of a given base frequency. For example, the base frequency may have a period of 100 nanoseconds, while the data pulses have periods of 200, 300, and 400 nanoseconds. The number of different pulse frequencies in the data signal also depends on the application.
The VC0 output frequency used during velocity lock is typically selected to be the base frequency of the data. The actual frequency used by the PLL circuit will typically be selected to be the fastest frequency of the data signals. In the example given above, the frequency actually used by the PLL circuit during velocity lock would be that having a period of 200 nanoseconds. The frequency selected can be generated by using a divide-by-N circuit applied with the VCO signal. For example, continuing the values in the example above, the VCO signal of 100 nanoseconds would be processed through a divide-by-2 circuit to give a signal having a period of 200 nanoseconds.
During phase lock, the VCO signal required by the PLL to decode the data is the base frequency signal. The typical method of supplying the PLL with both the VCO signal for phase lock and the divided-down VCO signal for velocity lock is to select the desired signal with a multiplexer. One circuit path through the multiplexer passes the VCO signal through a divide-by-N circuit to obtain the signal needed for velocity lock. The other circuit path through the multiplexer selects the VCO signal.
Multiplexing the VCO signal through non-identical circuitry introduces an undesirable phase step or phase shift in the multiplexer output signal, at the critical time when the PLL changes from velocity lock to phase lock. This phase step must be eliminated before the data may be decoded during phase lock. The time spent performing this phase step elimination task subtracts from the time available for velocity lock and increases the likelihood of invalid data or noisy data. When the VCO base frequency signal must be selected, it is possible to pass the VCO signal through components that approximate the delay of the divide-by-N circuit. This is an attempt to equalize the propagation delay of the data signal between the two data paths, but is only an approximation. Furthermore, multiplexers themselves usually are not perfectly matched along their two paths, especially in complementary metal oxide semiconductor (CMOS) technology. Thus, the phase step experienced when switching between velocity lock and phase lock is still present.